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Material engineering will become the main driving force of semiconductor miniaturization process

in October this year, Samsung announced that it took the lead in realizing the mass production of 10 nm FinFET process in the industry. Compared with the previous generation of 14 nm FinFET process, Samsung 10 nm process can achieve performance improvement of 27% or power consumption reduction of up to 40% on the basis of kostron R & D personnel reducing the foam pores to the micron level and reducing the chip size by up to 30%. This is the latest news about the next process node in the industry. Around this time, Intel and TSMC also announced ambitious development plans, and Moore's law is still moving forward firmly

in combination with this trend, applied materials company recently held a media meeting to introduce three semiconductor devices suitable for advanced technology to the media at one stroke: the applied provisiontm electron beam inspection system with a resolution of 1 nm, and the applied system that extends the application of tungsten through-hole contact metallization to the next generation of devices Endura@VoltaTMCVD W and Centura@iSprintTM Ald/cvd SSW, and applied to achieve atomic level etching accuracy Producer@SelectraTM System. Semiconductor technology will continue to develop in the future. 5 nm has been discussed by people. Material engineering technology will play an increasingly important role in this development process

10 nm and below processes, human single-chip microcomputer control faces new challenges

although the miniaturization of transistors has almost reached the extreme, the pace of progress of Moore's law has slowed down, from the previous month to the previous month, but from a technical point of view, the pace of progress has not slowed down. In fact, there have long been debates about how long Moore's law can last, but every time, because of the changes in key technologies, Moore's law continues to develop

according to Zhao ganming, chief technology officer of Applied Materials China, the development of super junction technology has promoted the development of 90nm process, stress engineering technology has promoted 90nm to 45nm node, ultra-low K technology has promoted the development of 45nm to 32nm, and high k metal gate is the key technology of 28nm

at present, semiconductor technology has entered the era of 16/14 nm and even 10 nm. New transistor types, together with problems such as mask, graphics, materials, process control and interconnection, will lead to many difficulties for the semiconductor industry in the future

"considering that the future devices will be limited in terms of chip size reduction, new materials, new device structures and the integration of various technologies must be adopted." Zhao ganming said. In the range of 16/14 nm to 7 nm, many problems need to be paid attention to for equipment and process, such as: everything related to the interface needs the cooperation of fine material engineering, film deposition can adopt atomic layer deposition (ALD) or selective film, even with crystal, etc. you'd better understand the lattice matching process in advance, and use dry method, selective removal and direct self-alignment methods to define the graphics. In other words, the current key technologies are closely related to the innovation of contact area and new interconnection materials

as for the future, people need to break through the technical challenges of SiGe channel or grid wound structure when it is below 5 nm. Intel company proposed the next generation transistor structure - nanowire FET, a FinFET with one side of the transistor surrounded by the gate, also known as ring gate FET, and has been defined by the international process roadmap itrs as a process technology that can realize 5 nm. At that time, the industry will face more problems, including physical and sensitivity requirements, and the introduction of new technologies and materials is inevitable

"with the evolution of semiconductor technology, material engineering will become the main driving force of future miniaturization technology." Zhao ganming pointed out

applied materials company intensively released products for advanced process equipment

in response to this trend, applied materials company introduced three products for 10 nm and 7 nm process nodes to the media at one fell swoop at the media meeting

according to Li Wensheng, senior process manager of Applied Materials China, as semiconductor technology has entered 10 nm and 7 nm nodes, the structure and defects of semiconductor devices are becoming smaller and smaller, and ordinary optical resolution instruments can no longer detect them. Multiple graphics technology has brought large-scale measurement needs, but 3D structure is difficult to detect defects. In order to solve these problems, the industry began to use electron beam testing equipment to solve these challenges

in response to this demand, Li Wensheng said that the newly launched provisiontm electron beam inspection system can provide a resolution accurate to 1 nanometer. At the same time, compared with the existing electron beam hot spot detection tool, the detection speed is increased by 3 times, which can ensure the accurate characterization, prediction and identification of defects affecting performance and yield in the whole product production cycle

wuguilong, a senior process engineer of Applied Materials China, introduced the innovative progress of material engineering in the contact area. In the previous technology node, due to the large size of the device, nucleation and flattening chemical vapor deposition (CVD) technology can be used for (W) filling. Nowadays, because the ultra-small opening at the plug is prone to overhang, the conformal stage of uniform growth on the film surface may be closed or clamped before filling, leaving holes. Even if there is no hole, because the filler grows from the side wall, a central gap will inevitably be formed in the middle during conformal deposition

in the process of making the jaw symmetrically clamp the sample as required, the contact area is an important bottleneck for improving the performance of the transistor, and it is also the main factor affecting the yield. How to deal with the challenge of reducing the volume of contact through holes, Wu Guilong said that the new product launched by applied materials company Endura@VoltaTM CVD W is the first new substrate layer used for tungsten filling in 10 years. Using tungsten filling can combine the barrier layer and the backing layer, increase the width of tungsten filling by three times to reach the critical size of 15 nm, simplify the process flow, effectively reduce the resistance of tungsten film (reduce the contact resistance by up to 90%), and improve the performance of transistors

applied at the same time Centura@iSprintTMALD/CVD can suppress the filling of crevice tungsten, which may generate filling from bottom to top without the problems of crevices and holes. Special pretreatment of the upper region of the nucleation layer can promote the growth of tungsten from bottom to top, so as to minimize the generation of holes or gaps in the contact area caused by pinch fracture

Zhao ganming also introduced the progress of Applied Materials Company in etching technology, which can realize atomic level accurate etching. With the increasingly complex structure of advanced microchips, the size of 3D logic chips and memory chips continues to shrink. An important barrier is to selectively remove a specific material from a multilayer structure without damaging other materials

"traditional wet etching is easy to destroy high aspect ratio devices and cannot penetrate small-size devices. Traditional dry etching lacks extreme tube selectivity and insufficient horizontal etching control ability. The newly launched selectratm system of applied materials company can selectively remove target materials without damaging other substances, which is very important for patterning and 3D structure." Zhao ganming said. Selectratm system is applicable to FinFET, gate wound (GAA), 3D NAND and DRAM devices to achieve atomic level etching accuracy of FinFET devices, and can support FinFET devices below 10 nm; Uniform lateral etching can be applied to 3D NAND devices; The DRAM and GAA devices can be removed without damage

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